[Freeswitch-users] Debian packages for ARM/MIPS/POWERPC

Wed Dec 16 02:25:04 MSK 2015

Stanislav,

Sometime in the next few days I need  to spend some quality time with that
code, out of sheer curiosity if for no other reason. There are a few things
in that code that have me - uh, stumped , to put it mildly.

Would you do me a favor,  and if you do hear back from the author /
maintainer,  let me know what he says? Or when he fixes it?

Thanks ,
Larry
On Dec 14, 2015 3:16 PM, "Stanislav Sinyagin" <ssinyagin at gmail.com> wrote:

> Larry, here it's just a pointer that is 16bit aligned, and is given to a
> function that tries to treat it as an array of 32bit values. See my new
> comment in the ticket. We just need the module author to fix this, as it's
> difficult to figure out why some ifdefs have "x" at the end.
> On 14 Dec 2015 19:03, "Larry Morley" <lmorley at neny.cslimits.net> wrote:
>
>> Stanislav,
>>
>> I saw that;  what I was saying was it looked to me like the processor was
>> interpreting data as code and it happened to work out that the bit pattern
>> for that data and for LDC/STC are the same.  I've run into problems before
>> where misaligned inductions have resulted in an ARM processor either
>> ignoring the improperly aligned portion of an instruction or treating it as
>> data.
>>
>> If you disassemble the code around where it traps, what  does the listing
>> show the processor is trying to execute?
>>
>> One additional thought - if you're concerned that calloc() or malloc() is
>> returning  a pointer that's improperly aligned,  you could always supply
>> your own temporarily  and see if the problem goes away.
>>
>> - Larry
>> On Dec 13, 2015 4:19 AM, "Stanislav Sinyagin" <ssinyagin at gmail.com>
>> wrote:
>>
>>> See the bottom of the bug description. There's a mismatch between a
>>> 16bit integer array and a function that treats it as array of 32bit floats.
>>> On 13 Dec 2015 3:30 am, "Larry Morley" <lmorley at neny.cslimits.net>
>>> wrote:
>>>
>>>> According to the ARM docs, the instruction in question decodes to
>>>> "coprocessor data transfer (LDC, STC)". The way that instruction is encoded
>>>> (with the first four bits == xE), the instruction will be executed every
>>>> time it's encountered (i.e., not conditionally).
>>>>
>>>> Stanislav, you said you thought the trap was related to HD math and not
>>>> alignment. Based on what that instruction apparently is, it looks to me
>>>> like you were on the right track.
>>>>
>>>> Do all ARM variants have an FPU, and if not, could this problem stem
>>>> from configure et al. determining there's an FPU on a platform where there
>>>> isn't one?
>>>>
>>>> Hope this helps someone find and eradicate this bug.
>>>>
>>>> - Larry
>>>> On Dec 12, 2015 7:04 PM, "Stanislav Sinyagin" <ssinyagin at gmail.com>
>>>> wrote:
>>>>
>>>>> https://freeswitch.org/jira/browse/FS-8651
>>>>> the source of the problem is quite deep in the sources of spandsp, so
>>>>> I can't offer a fix.
>>>>>
>>>>>
>>>>> On Thu, Dec 10, 2015 at 10:49 PM, Komar, Jason <jkomar at jbox.ca> wrote:
>>>>> > I get nothing in debug or sip trace. It always dies at
>>>>> mod_spandsp_fax so I
>>>>> > figured it was in that module. At that point freeswitch just restarts
>>>>> > without throwing any errors.
>>>>> >
>>>>> > Kernel log shows:
>>>>> >
>>>>> > Dec 10 14:16:17 antman kernel: [ 5949.832802] Alignment trap: not
>>>>> handling
>>>>> > instruction ecb17a01 at [<b44fe32c>]
>>>>> > Dec 10 14:16:17 antman kernel: [ 5949.834290] Unhandled fault:
>>>>> alignment
>>>>> > exception (0x001) at 0xb4546e4a
>>>>> >
>>>>> > The only part of the exception that is the same every time it
>>>>> happens is
>>>>> > "instruction ecb17a01."
>>>>> >
>>>>> > I would have just opened a JIRA, but I didn't think this was enough
>>>>> > information. I have been Googling trying to figure out how to get
>>>>> more info.
>>>>> >
>>>>> > Jason
>>>>> >
>>>>> >
>>>>> > On Thu, Dec 10, 2015 at 2:37 PM, Stanislav Sinyagin <
>>>>> ssinyagin at gmail.com>
>>>>> > wrote:
>>>>> >>
>>>>> >> Hi, I didn't see any errors, but I'm not using fax, and mostly it's
>>>>> >> bridging the calls and connecting users to a conference. Do you
>>>>> have more
>>>>> >> debugging information?
>>>>> >>
>>>>> >> Most probably the source of the problem is that x86 allows unaligned
>>>>> >> memory access: a word pointer can have any value. And other
>>>>> architectures
>>>>> >> don't allow this, and require the pointers to be aligned to word
>>>>> boundaries.
>>>>> >> Mongodb, for example, is known to fail on any non-x86 CPU because
>>>>> of that.
>>>>> >>
>>>>> >> So, probably mod_spandsp needs an audit.
>>>>> >>
>>>>> >> On 10 Dec 2015 21:11, "Komar, Jason" <jkomar at jbox.ca> wrote:
>>>>> >>>
>>>>> >>> Your instructions worked great for me building on/for my Odroid-U3
>>>>> (arm)
>>>>> >>> running Debian Jessie.
>>>>> >>>
>>>>> >>> I know you are running on arm at scaleway. Do you ever run into any
>>>>> >>> alignment issues? I'm getting alignment exception faults receiving
>>>>> faxes and
>>>>> >>> I'm having trouble pulling any useful debug messages.
>>>>> >>>
>>>>> >>> Thanks,
>>>>> >>> Jason
>>>>> >>>
>>>>> >>> On Mon, Nov 30, 2015 at 9:27 AM, Stanislav Sinyagin <
>>>>> ssinyagin at gmail.com>
>>>>> >>> wrote:
>>>>> >>>>
>>>>> >>>> hi,
>>>>> >>>>
>>>>> >>>> I put together the build scenario that I tested for ARM (armhf at
>>>>> >>>> scaleway.com), and it should also work for other architectures:
>>>>> >>>>
>>>>> >>>>
>>>>> >>>>
>>>>> https://freeswitch.org/confluence/display/FREESWITCH/Building+debs+for+other+architectures
>>>>> >>>>
>>>>> >>>> It will be great if someone tests them on other architectures too.
>>>>> >>>>
>>>>> >>>>
>>>>> >>>> cheers,
>>>>> >>>> stanislav
>>>>> >>>>
>>>>> >>>>
>>>>> >>>>
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