<p dir="ltr">Stanislav,</p>
<p dir="ltr">Sometime in the next few days I need to spend some quality time with that code, out of sheer curiosity if for no other reason. There are a few things in that code that have me - uh, stumped , to put it mildly.</p>
<p dir="ltr">Would you do me a favor, and if you do hear back from the author / maintainer, let me know what he says? Or when he fixes it? </p>
<p dir="ltr">Thanks ,<br>
Larry </p>
<div class="gmail_quote">On Dec 14, 2015 3:16 PM, "Stanislav Sinyagin" <<a href="mailto:ssinyagin@gmail.com">ssinyagin@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">Larry, here it's just a pointer that is 16bit aligned, and is given to a function that tries to treat it as an array of 32bit values. See my new comment in the ticket. We just need the module author to fix this, as it's difficult to figure out why some ifdefs have "x" at the end.</p>
<div class="gmail_quote">On 14 Dec 2015 19:03, "Larry Morley" <<a href="mailto:lmorley@neny.cslimits.net" target="_blank">lmorley@neny.cslimits.net</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">Stanislav,</p>
<p dir="ltr">I saw that; what I was saying was it looked to me like the processor was interpreting data as code and it happened to work out that the bit pattern for that data and for LDC/STC are the same. I've run into problems before where misaligned inductions have resulted in an ARM processor either ignoring the improperly aligned portion of an instruction or treating it as data. </p>
<p dir="ltr">If you disassemble the code around where it traps, what does the listing show the processor is trying to execute?</p>
<p dir="ltr">One additional thought - if you're concerned that calloc() or malloc() is returning a pointer that's improperly aligned, you could always supply your own temporarily and see if the problem goes away. </p>
<p dir="ltr">- Larry </p>
<div class="gmail_quote">On Dec 13, 2015 4:19 AM, "Stanislav Sinyagin" <<a href="mailto:ssinyagin@gmail.com" target="_blank">ssinyagin@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">See the bottom of the bug description. There's a mismatch between a 16bit integer array and a function that treats it as array of 32bit floats.</p>
<div class="gmail_quote">On 13 Dec 2015 3:30 am, "Larry Morley" <<a href="mailto:lmorley@neny.cslimits.net" target="_blank">lmorley@neny.cslimits.net</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">According to the ARM docs, the instruction in question decodes to "coprocessor data transfer (LDC, STC)". The way that instruction is encoded (with the first four bits == xE), the instruction will be executed every time it's encountered (i.e., not conditionally).</p>
<p dir="ltr">Stanislav, you said you thought the trap was related to HD math and not alignment. Based on what that instruction apparently is, it looks to me like you were on the right track.</p>
<p dir="ltr">Do all ARM variants have an FPU, and if not, could this problem stem from configure et al. determining there's an FPU on a platform where there isn't one?<br>
<br>
Hope this helps someone find and eradicate this bug.</p>
<p dir="ltr">- Larry</p>
<div class="gmail_quote">On Dec 12, 2015 7:04 PM, "Stanislav Sinyagin" <<a href="mailto:ssinyagin@gmail.com" target="_blank">ssinyagin@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><a href="https://freeswitch.org/jira/browse/FS-8651" rel="noreferrer" target="_blank">https://freeswitch.org/jira/browse/FS-8651</a><br>
the source of the problem is quite deep in the sources of spandsp, so<br>
I can't offer a fix.<br>
<br>
<br>
On Thu, Dec 10, 2015 at 10:49 PM, Komar, Jason <<a href="mailto:jkomar@jbox.ca" target="_blank">jkomar@jbox.ca</a>> wrote:<br>
> I get nothing in debug or sip trace. It always dies at mod_spandsp_fax so I<br>
> figured it was in that module. At that point freeswitch just restarts<br>
> without throwing any errors.<br>
><br>
> Kernel log shows:<br>
><br>
> Dec 10 14:16:17 antman kernel: [ 5949.832802] Alignment trap: not handling<br>
> instruction ecb17a01 at [<b44fe32c>]<br>
> Dec 10 14:16:17 antman kernel: [ 5949.834290] Unhandled fault: alignment<br>
> exception (0x001) at 0xb4546e4a<br>
><br>
> The only part of the exception that is the same every time it happens is<br>
> "instruction ecb17a01."<br>
><br>
> I would have just opened a JIRA, but I didn't think this was enough<br>
> information. I have been Googling trying to figure out how to get more info.<br>
><br>
> Jason<br>
><br>
><br>
> On Thu, Dec 10, 2015 at 2:37 PM, Stanislav Sinyagin <<a href="mailto:ssinyagin@gmail.com" target="_blank">ssinyagin@gmail.com</a>><br>
> wrote:<br>
>><br>
>> Hi, I didn't see any errors, but I'm not using fax, and mostly it's<br>
>> bridging the calls and connecting users to a conference. Do you have more<br>
>> debugging information?<br>
>><br>
>> Most probably the source of the problem is that x86 allows unaligned<br>
>> memory access: a word pointer can have any value. And other architectures<br>
>> don't allow this, and require the pointers to be aligned to word boundaries.<br>
>> Mongodb, for example, is known to fail on any non-x86 CPU because of that.<br>
>><br>
>> So, probably mod_spandsp needs an audit.<br>
>><br>
>> On 10 Dec 2015 21:11, "Komar, Jason" <<a href="mailto:jkomar@jbox.ca" target="_blank">jkomar@jbox.ca</a>> wrote:<br>
>>><br>
>>> Your instructions worked great for me building on/for my Odroid-U3 (arm)<br>
>>> running Debian Jessie.<br>
>>><br>
>>> I know you are running on arm at scaleway. Do you ever run into any<br>
>>> alignment issues? I'm getting alignment exception faults receiving faxes and<br>
>>> I'm having trouble pulling any useful debug messages.<br>
>>><br>
>>> Thanks,<br>
>>> Jason<br>
>>><br>
>>> On Mon, Nov 30, 2015 at 9:27 AM, Stanislav Sinyagin <<a href="mailto:ssinyagin@gmail.com" target="_blank">ssinyagin@gmail.com</a>><br>
>>> wrote:<br>
>>>><br>
>>>> hi,<br>
>>>><br>
>>>> I put together the build scenario that I tested for ARM (armhf at<br>
>>>> <a href="http://scaleway.com" rel="noreferrer" target="_blank">scaleway.com</a>), and it should also work for other architectures:<br>
>>>><br>
>>>><br>
>>>> <a href="https://freeswitch.org/confluence/display/FREESWITCH/Building+debs+for+other+architectures" rel="noreferrer" target="_blank">https://freeswitch.org/confluence/display/FREESWITCH/Building+debs+for+other+architectures</a><br>
>>>><br>
>>>> It will be great if someone tests them on other architectures too.<br>
>>>><br>
>>>><br>
>>>> cheers,<br>
>>>> stanislav<br>
>>>><br>
>>>><br>
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