[Freeswitch-dev] Wanpipe timing source - clock sharing

[Juraj Fabo]

Hi

I'm not sure whether this is a proper forum, but I have an issue with
wanpipe/dahdi driver and the sangoma a102de card.
My problem is probably the timing source change in case when the E1 cable is
disconnected from the card span or spans.
My application plays a PRI_CPE side and uses a testpattern/keepalive sending
on one dedicated e1 channel to detect E1 breakdown.
When there is no cable connected to particular span, keepalive algorithm
send patterns and reads 'dummy' data so it finds out that E1 is broken.
Actually I've read the info from wanpipe.spec about the free run mode in
firmware version V36, I use V37, here is my configuration

sles 11 SP1, wanpipe-3.5.23 (tested also 3.5.18), dahdi-2.5.0.1 (tested also
2.3.0.1), sangoma a102de, HWEC and DTMF detection off.

I have an experience with digium E1 cards and DAHDI driver that removing a
cable from E1 span
makes the span to receive a clock from another span connected to telko.
Or, given there is no other span connected to telko, to use internal clock
on all spans.
So on the digium with dahdi the clock source is moving from span to span as
specified
in "timing source" parameter of /etc/dahdi/system.conf (and indicated as
MASTER in the 1st line of /proc/dahdi/X)

I tested sangoma card together with wanpipe and dahdi drivers. Here the
behaviour was rather different.
When cable was removed, following messages were logged (amongst others)

Oct 21 09:34:06 v184 kernel: [ 3185.691989] wanpipe2: Lost of Signal is
detected!
Oct 21 09:34:10 v184 kernel: [ 3189.604230] wanpipe2:    LOF : ON
Oct 21 09:34:10 v184 kernel: [ 3189.604234] wanpipe2: E1 disconnected!
Oct 21 09:34:10 v184 kernel: [ 3189.604263] wanpipe2: AFT communications
disabled! (Dev Cnt: 2 Cause: Link Down)

Between time 09:34:06 and 09:34:10 my application still writes/reads to the
channel on span which was removed.
After 09:34:10 it is not possible to read/write anymore until the cable is
connected back
 (I use ACE framework event handler registered in reactor with READ | WRITE
| EXCEPT mask)

When last cable is removed (tested also with quad card) then the first span
'recovers' and read/write is possible on it.
Connecting one span 'enables' reading/writing on re-connected span.

I think this might be a timing source issue.
My question is, how to configure wanpipe/dahdi in order to share the clock
on all spans of sangoma,
also when there are spans which are configured and used by an application
but not connected.

Thank you in advance

Juraj Fabo
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